1. Field of the Invention
The present invention relates to a semiconductor integrated circuit design system, a semiconductor integrated circuit design method, a computer-readable recording medium for recording a semiconductor integrated circuit design program, and a method of manufacturing the semiconductor integrated circuit and, more particularly, a technology for carrying out a semiconductor integrated circuit design effectively by estimating interwiring capacitances with good precision prior to routing process.
2. Description of the Related Art
In the semiconductor integrated circuit in the deep submicron generation, it would be anticipated that capacitances between adjacent wirings and capacitances between intersecting wirings are increased. FIGS. 1A and 1B are views illustrating the capacitances between adjacent wirings and the capacitances between intersecting wirings. FIG. 1A shows a sectional model illustrative of a simple parallel plates in an ordinary semiconductor integrated circuit. In this model, a first layer aluminum wiring 12 is provided over a substrate 11 of the semiconductor integrated circuit along a directional perpendicular to the surface of the drawing, so that a wiring capacitance is generated between the substrate 11 and the aluminum wiring 12. FIG. 1B shows a sectional model illustrative of the capacitances between adjacent wirings and the capacitances between intersecting wirings. In this model, three first layer aluminum wirings 12 are provided over the substrate 11 of the semiconductor integrated circuit along the direction perpendicular to the surface of the drawing. In addition, a second layer aluminum wiring 13 is provided over three first layer aluminum wirings 12. Where a notation "capacitance between adjacent wirings" signifies an interwiring capacitance which is generated between adjacent parallel wirings while a notation "capacitance between intersecting wirings" signifies an interwiring capacitance which is generated between intersecting wirings. With the progress of miniaturization of the semiconductor integrated circuit, a distance between the substrate and the wiring and a distance between the wirings have been prone to be reduced. Accordingly, these interwiring capacitances have been increased.
FIG. 2 is a flowchart showing processes carried out by the semiconductor integrated circuit design method in the prior art. In this prior art, at first a logic design of the semiconductor integrated circuit has been carried out (step S400). Then, a layout design of the semiconductor integrated circuit which has been subjected to the logic design has been carried out (step S410). The layout design is made up of an automatic placement step S411 of executing the placements of necessary cells, etc. and an automatic routing step S412 of executing the wirings of the placed cells, etc. Subsequently, verification of the semiconductor integrated circuit which has been subjected to the layout design has been carried out (step S420). In this verification, an interwiring capacitance calculation has been executed (step S421) and also various verifications have been executed (step S422).
In general, inasmuch as it has not been defined which wirings should be provided in parallel with, or over/below respective wirings after the layout design has been finished, the capacitance between adjacent wirings and the capacitance between intersecting wirings cannot be calculated. Accordingly, these verifications have been carried out after the layout design of the wirings has been finished in the prior art.
As a result of these verifications, design of the semiconductor integrated circuit has been finished if requirements specification have been satisfied. In contrast, the process returns to the step S400 of logic design and the step S410 of layout design to thus carry out the design again unless requirements specification have been satisfied.
In this manner, in the design of the semiconductor integrated circuit in the prior art, there has been a problem such that, since the layout design and the logic design must be carried out once again according to the verification result, a design term has been extended.
In order to reduce the design term, performances of the semiconductor integrated circuit such as operating frequency, power consumption, etc. must be improved automatically. Therefore, the connectivity list and the layout of the semiconductor integrated circuit must be optimized by estimating precise interwiring capacitances including the capacitance between adjacent wirings and the capacitance between the intersecting wirings prior to the detailed routing, i.e., after the automatic placement or upon the automatic placement.
Meanwhile, such a method has been proposed that an "adjacent rate" and an "intersecting rate" of each chip are calculated to estimate the delay in the chip at the stage after the detailed routing has been finished (Patent Application Publication (KOKAI) Hei 8-110915, Inventor: Yukihiko Matsuda). However, the method in which the capacitances between adjacent wirings are considered at the stage before the cell placement have large estimation error and therefore is unsuitable for information to optimize each net. On the other hand, by the method in which the adjacent rate and the intersecting rate are estimated after the detailed routing, such rates cannot be used as information to optimize at the stage of the automatic placement or the automatic routing. More particularly, since the capacitances between adjacent wirings and the capacitance between intersecting wirings are optimized at the stage of the automatic placement or the automatic routing, they have not been able to be estimated after the cell placement has been completed but the wirings have not been provided yet.
Moreover, it has been known that the capacitances between adjacent wirings can be improved drastically by expanding the wire spacing. FIG. 3 is a graph showing the result of three-dimensional simulation indicating a relationship between an interwiring capacitance and an adjacent spacing. In FIG. 3, an abscissa denotes the adjacent spacing (.mu.m) and an ordinate denotes the interwiring capacitance (pF/mm). As shown in FIG. 3, the interwiring capacitance can be reduced if the adjacent spacing is enlarged by expanding the wiring interval. Hence, reduction in the delay has been tried by manual correction by imposing the wiring spacing constraint on respective wirings. Expansion of the net wire spacing has been employed widely in the layout design. Like this, in the method in which the wire spacing is extended only in a part of nets, since the wire spacing in most parts of nets has still remained narrow, the area of the semiconductor integrated circuit which is used for the wirings has not been so increased. However, the constraints has not been able to be generated based on the capacitances between adjacent wirings and the capacitance between the intersecting wirings which have been estimated prior to the automatic routing, to carry out the automatic layout.